# Where do you start with a PLL design for grid connect

I was having a conversation with an engineer about PLL design for grid connection. They were asking where to start? And I surprised them by talking about the grid coupling filter and what was the expected (power) angle jump over time between the grid and the converter when there was a grid fault.

And for those of you that don’t know I was asking about what the grid was expected to do. The question about the power angle pretty much sums up all you need to know about the grid. In the short term it gives you a really good indication of the X/R ratio, short circuit ratio and in the longer term the inertia on the grid. And once you have this information and throw in the grid ride through requirements and the voltage support requirements into a grid fault, only then can you start to think about the PLL response and requirements.

Things to remember are that your company wants the grid coupling filter to be as small as possible and as asymmetric as possible (outside L smaller than the inside L in your LCL) to keep the cost and DC bus voltage down while every other requirement I listed above pushes you in the other direction.

So how to choose. Two approaches are just guess or pull out your favourite power electronics analysis and simulation tools and get to work.

How do you know how much to put in your PLL? How do we manage the negative sequence? Do we need two PLLs? Are we decoupling the transient response. Can we control the power converter to make pure low THD current sinewaves when the grid has high THD voltages? All good questions but really nothing to do with anything PLL, but determined by the grid characteristics. And unfortunately the grid is a really nasty and varied place.

So finally we talked about harmonics and frequency coupling and it came up that PLLs have an annoying property of locking to or being disturbed by super and sub-harmonics of the grid frequency. This ended the conversation with a light-bulb moment on the engineers face. They rushed off to look at the super-harmonic’s effects on their PLL.

How do super and sub harmonics of the lock frequency have so much effect. Well the detector in the PLL is a multiplier so there is a modulation function. And that gets the super and sub harmonics involved. Mostly they are rejected but not always. Remember that your PLL isn’t a completely linear system.