If you are following the Zynq pathway for your new control platform for power electronics or another application then welcome to the Xilinx Zynq SoC adventure. The Zynq definitely is a great choice and has the benefits of being both a processor and an FPGA at the same time.
We have had Zynq SoCs at ELMG Digital Power for a about three years now and have been developing our competence. We have built up a Linux system on them in the past on one dev board. We are in the process of rebuilding it for another board for use with an LCD application. We are at the end of the process of moving our Spartan 6 IP cores onto 7 series (including Zynqs) for use in newer designs using the Vivado toolchain. We are also in the process of becoming certified Xilinx engineers through the Xilinx Alliance Program (XAP). This includes a large amount of training on the Zynqs directly from Xilinx.
ELMG Digital Power Membership of the Xilinx Alliance Program, XAP, means Zynq Asymmetric Multiprocessing know how and expertise.
Asymmetric Multiprocessing AMP
Asymmetric Multiprocessing a really powerful way of getting the best of both worlds (RTOS for real-time performance, Linux for ease of use, HMI and communications) on the one device. There are some pitfalls of using an RTOS for complex communication and Linux is not real-time. It is not trivial and comes with quite a few pitfalls and things that you must take care of. We have made some of these pitfalls so can help you with avoiding them.
These include the boot process and boot order as well as assigning which core is the ‘master’ and which is the ‘slave’. One of the main things to consider and plan out in an AMP system is resource allocation. Each core will need its own RAM whilst there must also be some shared RAM. Inter-processor communications will also need to be considered as well as peripheral access (both allocated and shared). Level 2 cache use also becomes more complicated. With correct planning and execution however, the Zynq AMP is the powerful tool that you need. Making full use of the capability is critical in getting a successful control system.
One of the great things about the Zynq System on Chip Asymmetric Multiprocessing AMP, is that certain engineers can do certain roles without knowing much about the Zynq as a whole. The HDL engineer can design modules with only knowing about the logic side and a software engineer can write code only knowing about the processor side. However, it is the bit in between which makes the Zynq so powerful and provides the magic that makes it run as a whole SoC. Getting data from the logic to the software in a timely manner is not as trivial as it sounds. One of the issues to be aware of is cache coherence. This is because the time it takes for the data to reach the software can range from clk cycles to hundreds even thousands of clock cycles depending on the interface used (for example it takes 25 clock cycles just to get to level 2 cache and many more if a DDR fetch is required). In control systems, this latency is important and choosing the correct interfaces for suitable data flow latency is key.
There are many of things to cover on the Zynq. This include partitioning who does what, logic or software?