Is there a student discount for the Digital Power Electronics Control Course?
In short the answer is no.
That said graduate students can benefit immensely from the course.
In the past students have attended and one of the students asked Dr.Laird to help with supervision in her PhD project on partial step filters for grid connected power converters. Dr Laird helped until her graduation in 2017.
The intention of the course is to provide industry training and to enable industry people. This means these attendees are the priority.
ELMG Digital Power invites you to register for our tailored training course, ‘Introduction to Advanced Digital Control of Power Electronics’
The workshop is in Camarillo, California.
Be among the best digital power electronics control engineers and get the best digital control of power electronics training.
This hands-on course aims to provide engineers with solutions to the key issues in digital signal processing, using microcontrollers, microprocessors, DSP and FPGA. These solutions can then be employed effectively in the digital control of power electronics.
Over the four-day course, split into morning and afternoon sessions, participants will be provided with targeted training on digital power electronics control covering the detail of both digital control and power electronics and how they go together. They will gain the ability to close a digital power converter feedback loop in a stable fashion by following repeatable easily understood steps, as well as techniques to understand what the effect digital control’s limited bandwidth, processing power, number of bits and dynamic range have in digital power electronic control.
Engineers who attend the course will gain in-depth knowledge of the interaction of power electronics and digital control; this includes sampling and aliasing in the context of fixed and variable frequency switching power converters. There will be take away methods and steps to solve design issues such as one sample noise, precision limits in filters and controllers, non-linearity, quantization and other digital effects. A copy of the slide slide presentation course booklet covering the material presented and lunch each day will be provided.
The course has been specifically designed to meet the learning needs of engineers, regardless of whether you are:
The course will be presented and led by Dr. Hamish Laird, Principal Engineer at ELMG Digital Power. An extremely well-regarded teacher, engineer, researcher and public speaker, Hamish works in developing digitally controlled power converters and controllers for converters. He is the author of seventeen academic papers on digital power electronics and power quality and has taught previous digital power courses at Camarillo.
ELMG Digital Power are continuing in the Xilinx Alliance Program.
After meeting the requirement to have Xilinx certified engineers we successfully completed the application for the program.
When asked about this Dr Laird said
“As part of ELMG Digital Power’s continuing commitment to providing fantastic service and products we are privileged in continuing our Xilinx Alliance Program membership. We see great things happening with Xilinx All Programmable FPGAs and Zynq SoCs. It was great to see the capability of the SDSoC tools and to see the progress and extension of the Vivado Suite. We are really pleased to continue our Xilinx Alliance Program commitment and are please to be part of the Xilinx community.”
Dr Laird continues
“We are very pleased and proud of our Xilinx Alliance Program membership and for the value that it lets us bring to our customers. Training for key people in our organization is essential for us to continue to help our customers with FPGA and other All Programmable solutions. Our IP blocks, power electronics know how and ability to deliver solutions are our key areas of focus.”
See you at APEC 2018 next week. Here is the ELMG Digital Power APEC 2018 Presentation Schedule. Join us and Ridley Engineering at Booth #1025 at APEC.
Monday March 5th
5:00pm Show opening
6:00 pm Running RidleyWorks
7:00 pm Beyond Small-Signal Models
7:30pm Digital Control – What goes Wrong?
Tuesday March 6th
12:00pm Show opening
12:30pm Proximity Loss Models
1:30pm Rapid prototyping with SwitchBit
2:30pm Precision extension in digital integrators – how and why?
4:30pm Dead time compensation in DC to DC converters
Wednesday March 7th
10:00am Show opening
10:30am Ridley Engineering Hands-on Workshop
11:30am Designing your converter so you can control it with digital control
12:30am Ridley Engineering Internship Program
1:00pm RidleyWorks Game Final
See you at APEC in San Antonio, Texas.
Recently I needed to build U-Boot for the Picozed. Mainly because we needed to get our control platform running on another Picozed variant but also to de-risk part of our process. For those of you that don’t know the control platform (called the Fyfe) is made from our IP blocks is in the Zynq fabric with Linux running on the Zynq A9 cores as the software host. This gives us dedicated FPGA speed real time control in the fabric and all the good things that Linux provides such as networking, scripting , python and the like. We use a PicoZed as the System on Module (SoM) for our control platform. So this is the first post in the article series Building U-Boot Picozed.
U-Boot is the ubiquitous boot loader for booting Linux. It can be used to boot other systems as well but I just needed to create a U-Boot that would get me up and running on the Picozed. Building U-Boot had never been my thing but it was decided that I should build and learn it for myself.
U-Boot or more correctly Das U-Boot is supported and maintained by the people at https://www.denx.de/wiki/U-Boot.
As an aside I think that the name Das U-Boot is a reference to the 1981 movie Das Boot about a U boat submarine. This is a great movie with superb German dialog version. Check it out. Information on the movie is here https://en.wikipedia.org/wiki/Das_Boot. The German language version is the better version.
So as I have been doing this whole software development thing for a while and as always the first thing I did was ask an expert. It is always good to ask an expert. It actually doesn’t matter which expert as the experts generally all know each other.
I asked Adam Taylor from Aduivo Engineering and of Microzed chronicle fame. He helps with tricky FPGA issues and also helps with our IP blocks and test-benches. Adam, it turns out, is not a U-Boot guy but recommended a number of people. He also put a LinkedIn post out for me. And I got recommended through Adam T. to Matteo Vit. Matteo is extremely helpful.
So I need to fill in some of the story as to how I was constrained. We have this one client who likes Vivado 2016.2 and so we have residual development and support requirements that are in Vivado 2016.2. Vivado moves on regularly and it generally gets better. At the moment on my Linux laptop I have Vivado 2016.2, 2016.4, 2017.1 and 2017.2 all installed and all with projects. I also have SDK for all these Vivado varients also. I run straight Ubuntu 16.04 and all the Vivado versions go.
The risks of updating to new versions or providing support with historic Vivado versions are really beyond what I want to get into here. I hope to write another blog series about that later.
Before we built U-Boot we needed the FSBL. Before I did this I asked about whether this was the best way to go forward.
I also consulted with Charles M. who is a very good Linux and U-Boot guy, a really good consultant on flash memory usage and also he is great company. He proposed that I take the SPL route to U-Boot. The SPL approach is where the processor configuration is done by including the hardware specific initialization code (ps7_init_gpl) into the U-Boot build. This SPL is not officially supported by Xilinx for the Zynq U-Boot release. The Xilinx description of the process is here http://www.wiki.xilinx.com/U-Boot+Secondary+Program+Loader. I did not pursue this SPL but I plan to go through this process in the future for completeness.
It’s clear when you look at it that the U-Boot version and the Linux version need not be the same. This was a really big realization for me. And an important realization for those building Linux systems.
U-Boot is a boot-loader and it moves the binaries of the kernel, ramdisk and device tree from storage media to memory. That is all it does. U-Boot isn’t actually a Linux specific program.
So some of you will be wondering why I am writing this as the PicoZed must have an off the shelf from the git repo U-Boot version that just goes? I found that the answer to this is no. The U-Boot build when I selected PicoZed for the make option from the repo I pulled from the xilinx git did not work on a PicoZed. I also found that the defconfig used for the picozed (don’t worry if you don’t know what that is I’ll get to that in a follow up blog) was not correctly setup to support the flash memory on the PicoZed.
Well this was a surprise.
So as a relative new U-Boot software user I decided that I would build U-Boot for the PicoZed myself and share the process with you. I take the FSBL approach so what I do is compatible with the Xilinx supported U-Boot. And I got it working. Over the next couple of months I will show you what I have learned in building U-Boot.
ELMG Digital Power are offering you the opportunity to attend our regular webinar on Digital Control in Power Electronics. This month’s webinar is titled “Frequency Responses for Control”.
This is an hour webinar covers
Thursday 12th October at 12 noon California time (3pm Eastern).
Join ELMG Digital Power’s regular monthly Digital Power Webinar and expand your Digital Power knowledge and expertise.
The webinar will be hosted and presented by Dr. Hamish Laird. Hamish is ELMG Digital Power’s CTO and presenter and teacher of the Digital Control of Power Electronics Workshop. He has 25 years experience the design and implementation of varied digital control systems and IP for power electronics.
This exciting opportunity is free and includes a 15 minute Q&A session with Dr. Hamish.
The webinar is scheduled for Thursday 12th October at 12 noon California time (3pm Eastern).
Click the link below to register. Spaces are limited.