Posts Tagged ‘Zynq’

Building U-Boot PicoZed

Tuesday, January 2nd, 2018

Recently I needed to build U-Boot for the Picozed.  Mainly because we needed to get our control platform running on another Picozed variant but also to de-risk part of our process. For those of you that don’t know the control platform (called the Fyfe) is made from our IP blocks is in the Zynq fabric with Linux running on the Zynq A9 cores as the software host.  This gives us dedicated FPGA speed real time control in the fabric and all the good things that Linux provides such as networking, scripting , python and the like.  We use a PicoZed as the System on Module (SoM) for our control platform.  So this is the first post in the article series Building U-Boot Picozed.

Building U-Boot PicoZed

U-Boot is the ubiquitous boot loader for booting Linux.  It can be used to boot other systems as well but I just needed to create a U-Boot that would get me up and running on the Picozed.  Building U-Boot had never been my thing but it was decided that I should build and learn it for myself.

U-Boot or more correctly Das U-Boot is supported and maintained by the people at  https://www.denx.de/wiki/U-Boot.

Submarines

As an aside I think that the name Das U-Boot is a reference to the 1981 movie Das Boot about a U boat submarine.  This is a great movie with superb German dialog version.  Check it out.  Information on the movie is here https://en.wikipedia.org/wiki/Das_Boot.  The German language version is the better version.

Help!

So as I have been doing this whole software development thing for a while and as always the first thing I did was ask an expert.  It is always good to ask an expert.  It actually doesn’t matter which expert as the experts generally all know each other.

I asked Adam Taylor from Aduivo Engineering and of Microzed chronicle fame.  He helps with tricky FPGA issues and also helps with our IP blocks and test-benches.  Adam, it turns out, is not a U-Boot guy but recommended a number of people.  He also put a LinkedIn post out for me.  And I got recommended through Adam T. to Matteo Vit.  Matteo is extremely helpful.

FSBL

So I need to fill in some of the story as to how I was constrained.  We have this one client who likes Vivado 2016.2 and so we have residual development and support requirements that are in Vivado 2016.2.  Vivado moves on regularly and it generally gets better.  At the moment on my Linux laptop I have Vivado 2016.2, 2016.4, 2017.1 and 2017.2 all installed and all with projects.  I also have SDK for all these Vivado varients also.  I run straight Ubuntu 16.04 and all the Vivado versions go.

The risks of updating to new versions or providing support with historic Vivado versions are really beyond what I want to get into here.  I hope to write another blog series about that later.

Before we built U-Boot we needed the FSBL.  Before I did this I asked about whether this was the best way to go forward.

SPL or not?

I also consulted with Charles M. who is a very good Linux and U-Boot guy, a really good consultant on flash memory usage and also he is great company.  He proposed that I take the SPL route to U-Boot.  The SPL approach is where the processor configuration is done by including the hardware specific initialization code (ps7_init_gpl) into the U-Boot build.  This SPL is not officially supported by Xilinx for the Zynq U-Boot release.  The Xilinx description of the process is here http://www.wiki.xilinx.com/U-Boot+Secondary+Program+Loader.  I did not pursue this SPL but I plan to go through this process in the future for completeness.

Which U-Boot version?

It’s clear when you look at it that the U-Boot version and the Linux version need not be the same.  This was a really big realization for me.  And an important realization for those building Linux systems.

U-Boot is a boot-loader and it moves the binaries of the kernel, ramdisk and device tree from storage media to memory.  That is all it does.  U-Boot isn’t actually a Linux specific program.

U-Boot for PicoZed – should just work right?

So some of you will be wondering why I am writing this as the PicoZed must have an off the shelf from the git repo U-Boot version that just goes?  I found that the answer to this is no.  The U-Boot build when I selected PicoZed for the make option from the repo I pulled from the xilinx git did not work on a PicoZed.  I also found that the defconfig used for the picozed (don’t worry if you don’t know what that is I’ll get to that in a follow up blog) was not correctly setup to support the flash memory on the PicoZed.

Well this was a surprise.

So as a relative new U-Boot software user I decided that I would build U-Boot for the PicoZed myself and share the process with you.  I take the FSBL approach so what I do is compatible with the Xilinx supported U-Boot.  And I got it working.  Over the next couple of months I will show you what I have learned in building U-Boot.

 

 

 

 

 

 

Control Scope Integrated into Digital Power Controller

Friday, July 8th, 2016

How can I look at my digital signals in my power controller?

One of the big issues when working on digital control of power electronics is being able to look at the digital signals inside your controller.  In order to see what is going on inside the control the digital signals need to be brought out so you can look at them.

When a DAC isn’t good enough.

One way to do this is with a digital to analog converter (DAC) where the digital stream is sent out as an analogue signal.  These DAC channels are really useful and should be on every digital power electronics controller.  However processing power usually limits the logging or data streaming to a DAC to a low number of channels.  Each channel requires a scope channel of its own to do measurement.  Any measurement is limited in length to the scope’s memory and the scopes sample rate.

scope-capture

ELMG Digital Power ControlScope

Data Collection in the Controller and Detecting Events

There is also the issue that collecting enough data to allow event detection such as;

  • single sample errors
  • clipping
  • overflow
  • underflow or precision loss and
  • bursty instability due to precision loss

can be a very difficult large load on the control processor and memory if the data logging rate is very high or if the rate of the problem is very low.

Control Scope Integrated into Digital Power Controller

To solve this problem we put the data collection and logging into the controller but without loading the controller.

Using the Xlinx Zynq system on a chip (SoC) we use the flexibility of running Linux on one of the two ARM 9 cores to provide the high speed gigabit Ethernet connectivity.

Dlog Implementation

Dlog Implementation

We also use the Linux for secure remote access if required.

Using ELMG Power Core IP blocks and know how we create firmware in the FPGA fabric of the Zynq.  This connects to the Linux kernel and then the Linux user space.  Data can be logged at full sample rates into SD cards or MMX memory and simultaneously out via the Gigabit Ethernet to the internet.

To be very clear no Linux code is included in the power electronics control function which is all implemented in the FPGA fabric on the Zynq.

Put a scope on the other end of the Ethernet

The video shows the ELMG ControlScope application connected to the ELMG Digital Power Zynq data collection system (named Dlog).

This system implements a fully functional oscilloscope that allows the internal operation of the digital control to be shown and logged.

With gigabit Ethernet logging rates of 25 M bytes per second are possible using Dlog.

This means that logging of your power converter performance and waveforms, scope function or debugging can be done over the internet.

To evaluate the Dlog and the ControlScope than click below.  


Request Dlog and ControlScope Information



Free Webinar on Digital Power using Zynq

Sunday, July 3rd, 2016

On Tuesday 12thJuly, we would like to offer you the opportunity to learn about Digital Power using Xilinx Zynq SoC.

Join ELMG Digital Power (Members of the Xilinx Alliance Program) for their Free Zynq Digital Power Webinar and expand your knowledge and expertise by discovering:

  • What is important in digital power, including numeric precision and latency
  • How to design a compensator in the digital domain
  • Why you would use a FPGA for digital power and why the Zynq SoC in particular
  • Key issues in digital controllers in programmable logic, such as the serial-parallel trade-off, fixed or floating point, choosing sample rates and what precision to use
  • The building blocks for digital control and ELMG’s licensable IP cores
  • IIR digital filter design (a case study) along with understanding the delta operator
  • Using the ARM cores in the Zynq to your full advantage.
Free webinar on digital power using zynq

Xilinx Zynq SoC is a great processor for digital power electronics control.

Dr. Tim King presents

The free webinar on digital power using Zynq will be hosted and presented by Dr. Tim King, ELMG Digital Power’s Principal FPGA Engineer. Tim has considerable experience the design and implementation of varied digital control systems and IP for power electronics on FPGA platforms.

This exciting opportunity is free and includes a short Q&A session with Dr. Tim King.

Dr Tim King - Free Webinar on Digital Power using Zynq

Dr Tim King

When and where

The webinar will be held on 12th July and is available globally in your time zone. Just choose a time that best suits you from these three options:

Spaces are limited.

July 12th 2016 – commencing at 9am London, England. 1000 (10am) Berlin Germany.


Register for Europe

 

July 12th 2016 – commencing at 1pm San Francisco, 3pm Houston, 4pm New York.




Register for USA

 

July 12th 2016 – commencing at 4pm in Christchurch New Zealand, 2pm Sydney Australia, 1pm Tokyo Japan, and 9:30am New Delhi, India





Register for Asia-Pacific




If you cannot attend at the scheduled time then register now and watch the recording later.

Spaces are limited.

Zynq System on Chip Asymmetric Multiprocessing AMP

Saturday, August 29th, 2015

If you are following the Zynq pathway for your new control platform for power electronics or another application then welcome to the Xilinx Zynq SoC adventure.  The Zynq definitely is a great choice and has the benefits of being both a processor and an FPGA at the same time.

We have had Zynq SoCs at ELMG Digital Power for a about three years now and have been developing our competence.  We have built up a Linux system on them in the past on one dev board.  We are in the process of rebuilding it for another board for use with an LCD application. We are at the end of the process of moving our Spartan 6 IP cores onto 7 series (including Zynqs) for use in newer designs using the Vivado toolchain.  We are also in the process of becoming certified Xilinx engineers through the Xilinx Alliance Program (XAP).  This includes a large amount of training on the Zynqs directly from Xilinx.

 

XAP Membership brings Zynq AMP benefits to ELMG Digital Power

ELMG Digital Power Membership of the Xilinx Alliance Program, XAP, means Zynq Asymmetric Multiprocessing know how and expertise.

Asymmetric Multiprocessing AMP

Asymmetric Multiprocessing a really powerful way of getting the best of both worlds (RTOS for real-time performance, Linux for ease of use, HMI and communications) on the one device.  There are some pitfalls of using an RTOS for complex communication and Linux is not real-time.   It is not trivial and comes with quite a few pitfalls and things that you must take care of.  We have made some of these pitfalls so can help you with avoiding them.

These include the boot process and boot order as well as assigning which core is the ‘master’ and which is the ‘slave’.  One of the main things to consider and plan out in an AMP system is resource allocation.  Each core will need its own RAM whilst there must also be some shared RAM.  Inter-processor communications will also need to be considered as well as peripheral access (both allocated and shared).  Level 2 cache use also becomes more complicated.  With correct planning and execution however, the Zynq AMP is the powerful tool that you need. Making full use of the capability is critical in getting a successful control system.

One of the great things about the Zynq System on Chip Asymmetric Multiprocessing AMP, is that certain engineers can do certain roles without knowing much about the Zynq as a whole.  The HDL engineer can design modules with only knowing about the logic side and a software engineer can write code only knowing about the processor side.  However, it is the bit in between which makes the Zynq so powerful and provides the magic that makes it run as a whole SoC.  Getting data from the logic to the software in a timely manner is not as trivial as it sounds.  One of the issues to be aware of is cache coherence.  This is because the time it takes for the data to reach the software can range from clk cycles to hundreds even thousands of clock cycles depending on the interface used (for example it takes 25 clock cycles just to get to level 2 cache and many more if a DDR fetch is required).  In control systems, this latency is important and choosing the correct interfaces for suitable data flow latency is key.

There are many of things to cover on the Zynq.  This include  partitioning who does what, logic or software?

Demonstration of a simple car dash on 7z010 Zynq SoC

Saturday, August 29th, 2015

This demonstration of a simple car dash on 7z010 Zynq SoC from Xilinx implements an touch screen automotive car dash cluster with speedometer and rev counter.

 

The hardware target is the Avnet MicroZed which is mounted on a carrier board.  The LCD is a seven inch touch display.

 

We put this together using the Xilinx Vivado Design Suite.

Contact us for touch screen and display solutions using Zynq.

P.S. Subscribe to ELMG Digital Power on Youtube

Contact us for touch screen and display solutions using Zynq.