The uniqueness of the Digital Control Workshop is that it is not focussed on one microcontroller family. We cover the key know how that ensures you and your team will get your digital power supply robust and reliable.
Here at ELMG Digital Power our platform is an FPGA based power converter controller that we have developed. We sell power electronic specific FPGA IP blocks for PWM, filters, three to two blocks and all the other required power electronic blocks.
We have development experience in using processors for power electronics control from
Our course came about when and R and D manager asked us why his team had knowledge gaps that we were now helping fix. These gaps were common across a number of our OEM clients. We address these key common knowledge gaps in the course.
Happy to have a netmeeting or skype call to talk through this at anytime.
This year the APEC was in Tampa and ELMG Digital Power’s Hamish Laird presented a Professional Education Seminar.
This coming month, on Thursday July 27 at 12 noon California time (3pm Eastern) ELMG Digital Power are offering you the opportunity to attend an hour webinar of the three part ELMG Digital Power APEC 2017 Professional Education Seminar. (This is the second in a three part presentation.)
Join ELMG Digital Power’s regular monthly Digital Power Webinar and expand your Digital Power knowledge and expertise.
As part of their commitment to the Xilinx Alliance Program Certification ELMG Digital Power CTO and founder, Dr. Hamish Laird has completed Xilinx Certification.
When asked about this Dr Laird said
“As part of ELMG Digital Power’s continuing commitment to Xilinx, the Xilinx Alliance Program and the fantastic technology that Xilinx provides I am excited to complete this training and achieve Certification. We see great things happening with Xilinx All Programmable FPGAs and Zynq SoCs. It was great to see the capability of the UltraScale technology and to see the progress and extension of the Vivado Suite. We are really pleased to continue our Xilinx Alliance Program commitment and are please to be part of the Xilinx community.”
Dr Laird continues
“We are very pleased and proud of our Xilinx Alliance Program membership and for the value that it lets us bring to our customers. Training for key people in our organization is essential for us to continue to help our customers with FPGA and other All Programmable solutions. Our IP blocks, power electronics know how and ability to deliver solutions are our key areas of focus.”
“I was looking through ELMG’s tutorial “Three Key Issues to Watch out for in the Digital Control of Power Electronics” (http://www.elmgdigitalpower.com/power-electronics-digital-control-free-report-on-three-key-issues/) and am having some trouble understanding the relationship between frequency, register size, and equivalent bits.
An example given in the “2. Timer Precision” section of the document reads:
‘Consider the case where the timer clock runs at 40MHz. If the variable period oscillator register has 256 bits then the maximum frequency that the VPO can make is 10MHz and the minimum is 39.0625kHz. The example LLC resonant power converter needs a variable frequency of 500kHz to 210kHz to perform the control. This means the VPO count register has a usable range from 80 to 191. This is 111 counts which is 6.8 equivalent bits or almost seven bits.”
Equivalent bits are a great way to look at numeric precision.
Come join the discussion to see how equivalent bits is calculated. https://www.linkedin.com/groups/6677852/6677852-6242781250545942530
I’ve got a situation where I have a generator hooked up to a rectifier doing space vector control. The rectifier has an LC filter. Inductor current and cap voltage is measured. The L from the generator makes up the second L. I didn’t put a virtual damper in the fpga code (like I should have) and am trying different things. This is only a prototype so just working is the main thing. Which would be the best way to go in my current situation?
*pole cancellation in the digital controller (in dq and 0 components)
*Adding a physical damping resistor to the filter cap
*increasing filter cap
*removing filter cap (voltage Pll seems to track fine on HIL and simulation but haven’t tried on power hardware)
Sorry about posting too much, but I’m thankful for any suggestions!