Xilinx Zynq can do asymmetric multiprocessing. Is that why you would use them in digital power control? Asymmetric multiple processing is great for a digital power controller because it allows you to do a Real Time Operating System on one core. This is where you can do your control tasks or you can use this core in conjunction with the FPGA logic to do your control. This means you can use the high precision and the high performance of the FPGA logic to implement the control. It also has the ability to do the low level, effectively bit bashing, which software is not every good at doing.
The other advantage with asymmetric multiprocessing is that you can put Linux on the other core. Having Linux on the other A9 core allows you to do stuff like Ethernet and possibly CAN in automotive, UARTs and other serial communications very simply. This is because all that has been done. The implementation of the function is an exercise in scripting. It is very simple to work in this Linux application space.
Getting the data from the Real Time Operating System or FPGA logic to the Linux system can be done with the shared memory on the Zynq. Beware of possible issues around caching when taking this approach. Another feature of the Zynq is the cache coherent accelerated coherency port. This allows you to get cache coherent data from the FPGA logic control system into your Real Time Operating System.
If you have a large legacy software code library you can leverage it by porting this to the real time core. This does not take full advantage of the Zynq. However one way to make use of legacy code is to take the more complicated parts and put them into the FPGA logic. This can be done one function at a time so validation of function is possible along the development path.
Getting data from the Zynq logic fabric to the cores is not overly difficult. It is done by writing to one memory location and reading from another. The challenge is to make sure that the memory reads and writes are to the correct locations that is not being write accessed by the other core. Coherence is an always present issue in multicore processing. Managing the memory to achieve this is what the ELMG Digital Power FABRIC2PROCESSOR IP Core does.
So where do you start in developing a power converter platform? At ELMG Digital Power we start in the FPGA logic. We take some of the ELMG Digital Power IP Cores which provide functions including:
All the power control is in the FPGA fabric and the cores provide supervisory function and network connection.
The number of bits in analogue to digital converters (ADC) can mean:
This potentially leads to the digital filter failing to operate on small inputs. FPGA based systems such as Zynq systems on chip allow the number of bits in the control to be set to what is suitable.
Pulse width modulator (PWM) or variable frequency/period oscillator (VFO/VPO) operate from timers with a set time resolution from the clock. That means time is quantized.
The period or duty of the oscillation or modulator cannot vary continuously as it can for its analogue equivalent.
Commonly, going to digital control requires a new power converter development as opposed to swapping analogue control for digital while leaving the converter the same.
This is because reductions are typically required for: