ELMG use a partition approach to product development.
This hierarchical top down approach divides the system into manageable blocks. Each block can be designed, coded and verified independently.
The partition process creates
Interface specifications and
for each block.
The overall hardware system is determined. From here the interfaces to the FPGA are defined to determine the I/O count requirements.
Hardware system partition with FPGA shown at the center.
FPGA Internal Architecture
Internal architecture of the FPGA is designed. Typically this is a functional partition that minimizes the interconnections between the blocks.
Internal Architecture for FPGA
FPGA Code Tree
The code tree of the partition creates a hierarchy of code modules. Each module is designed and coded. It is also tested using a module level testbench.The integration process starts at the bottom of the module tree and rises to the top.
Each integration is tested with an testbench.
An ELMG Digital Power Code Tree.
FPGA Process Structure
The architecture is completed by the a process view where data flow and control flow architecture is made clear.