FPGA Design Optimisation

ELMG review service ensure quality design, implementation and verification of FPGA design.  This wrap around service ensures

• Design review
• Quality deliverables
• Verification coverage
• Functional validation and
• Confidence

Verification and validation of FPGA code and integration is always a significant part of development.  To ensure that the deliverd code is well controlled ELMG use a robust and traceable process for release.  When a customer was struggling to release quality code and having to repeatedly release we provided training and advice.  A senior ELMG Digital Power FPGA Engineer spent a week working though the code release using  a formal process that is now adopted as the clients standard way to release FPGA designs.

FPGA system performance improvement case study.

It won’t fit in the FPGA
When our customer could not fit their design into a cost effective FPGA they call us.  We reviewed the design and coding of the system  We identified that large numbers of signals crossed clock domains.

Clock Domain Crossing
Synchronisation across clock domains in FPGA is required to avoid metastability.  The resources necessary to achieve this for wide data paths can be large.

Solution!
In order to reduce the synchroniser resource use ELMG FPGA engineers used a dual port ram clock domain crossing solution.  This reduced FPGA fabric use by 10%.

It fits now
The result was that the FPGA size required was minimised and so kept cost effective.