Output from the Xilinx FPGA tool for a Phase Locke Loop implemented with a cordic block.
This entry was posted on Thursday, April 10th, 2014 at 2:51 am and is filed under .
You can follow any responses to this entry through the RSS 2.0 feed.
You can leave a response, or trackback from your own site.
Mail (will not be published) (required)