Archive for the ‘Zynq’ Category

Free Webinar on Digital Power using Zynq

Sunday, July 3rd, 2016

On Tuesday 12thJuly, we would like to offer you the opportunity to learn about Digital Power using Xilinx Zynq SoC.

Join ELMG Digital Power (Members of the Xilinx Alliance Program) for their Free Zynq Digital Power Webinar and expand your knowledge and expertise by discovering:

  • What is important in digital power, including numeric precision and latency
  • How to design a compensator in the digital domain
  • Why you would use a FPGA for digital power and why the Zynq SoC in particular
  • Key issues in digital controllers in programmable logic, such as the serial-parallel trade-off, fixed or floating point, choosing sample rates and what precision to use
  • The building blocks for digital control and ELMG’s licensable IP cores
  • IIR digital filter design (a case study) along with understanding the delta operator
  • Using the ARM cores in the Zynq to your full advantage.
Free webinar on digital power using zynq

Xilinx Zynq SoC is a great processor for digital power electronics control.

Dr. Tim King presents

The free webinar on digital power using Zynq will be hosted and presented by Dr. Tim King, ELMG Digital Power’s Principal FPGA Engineer. Tim has considerable experience the design and implementation of varied digital control systems and IP for power electronics on FPGA platforms.

This exciting opportunity is free and includes a short Q&A session with Dr. Tim King.

Dr Tim King - Free Webinar on Digital Power using Zynq

Dr Tim King

When and where

The webinar will be held on 12th July and is available globally in your time zone. Just choose a time that best suits you from these three options:

Spaces are limited.

July 12th 2016 – commencing at 9am London, England. 1000 (10am) Berlin Germany.


Register for Europe

 

July 12th 2016 – commencing at 1pm San Francisco, 3pm Houston, 4pm New York.




Register for USA

 

July 12th 2016 – commencing at 4pm in Christchurch New Zealand, 2pm Sydney Australia, 1pm Tokyo Japan, and 9:30am New Delhi, India





Register for Asia-Pacific




If you cannot attend at the scheduled time then register now and watch the recording later.

Spaces are limited.

Migration from MCU/DSP to FPGA for Power Electronics: Part 1 Software

Tuesday, November 17th, 2015

In a recent discussion we were asked about the migration path from MCU/DSP to FPGA.

“I am probably not alone when I use MCU/DSP devices to implement control algorithms, protection, logic etc to control the power hardware, using code such as ASM, C or C++, but want the advantages of FPGA. What suggestions do you have to start this migration, both in terms of a cheap evaluation board, and software tools, that can be targeted at driving various topologies and speeds.”

Thanks to Anthony W. for the question.  We get asked similar migration from MCU/DSP to FPGA for power electronics questions where the emphasis is more about retaining the value of an existing code base and coding team expertise while leveraging the flexibility of the FPGA.

As the first question states MCU/DSP devices are a common tool to implement control algorithms, protection, logic and sequencing for  control power hardware, using code such as ASM, C or C++.  However they do not have the power and flexibility of FPGAs. What is the best way to approach a migration from MCU/DSP to FPGA, both in terms of evaluation boards, and software tools, for a wide range of power electronic applications?

Best migration path MCU/DSP to FPGA for Power Electronics

There are a number of pathways to do this. The first one is High Level Synthesis. This is basically writing FPGA code in C. It is a very powerful tool but it does take some know how to make sure that you can get the most benefit out of the transition to FPGA. The downside of this is that it is quite expensive. There are however a couple of FPGA kits out there that do come with a kit-locked license (node-locked and locked to the FPGA model on the board).

Processor Inside

Another way is to use an FPGA with a processor, or processors, inside it. These processor can be soft-cores like Xilinx’s Microblaze or hard-cores like the twin ARM A9s in Xilinx’s Zynq series. (Reports on FPGA development projects show that almost 50% have some sort of processor.)  This processor allows you to directly port your code from your MCU/DSP to the Zynq/Microblaze and be ready to go. This may seem counter-productive as going from one processor to another without really gaining FPGA power is work for no reward.  The advantages come when you move parts of your code (the high intensity tasks such as the control algorithms) from C to the FPGA hardware. This provides a power boost for the important parts of your code whilst still having the simplicity of C for the easy flow of your code. A good analogy would be that the FPGA parts are the equivalent of the ASM parts on the MCU/DSP but with the superman type speed advantage of doing things in parallel in the FPGA fabric.

Best of both

Xilinx has also combined the HLS and the C coding options with their SDSoC product. It is designed for the Zynq SoC .  The coding is done in C. However you can use HLS to accelerate certain parts of the code for you to gain the most benefit.

Getting the most out of the Zynq solution does require either the expensive HLS toolchain and training in that or writing your own HDL. Another option is to purchase IP that other companies have written.  This allows you to create a fast and efficient system without needing to know coding of an FPGA in HDL or C.  ELMG Digital Power has a large suite of power electronics IP to get your application off the ground fast.

Prototyping and Development Platforms

In part 2 of this blog post, which is coming later, the answers to the questions

“How can I prototype this when the chip is BGA only?”

and

“What is an appropriate development platform or dev board?”

are covered.

Download the report ‘Your Digital Power Future – Roadblocks to Avoid’ to learn about the three key issues to watch out for in the Digital Control of Power electronics.


Download report now

Zynq System on Chip Asymmetric Multiprocessing AMP

Saturday, August 29th, 2015

If you are following the Zynq pathway for your new control platform for power electronics or another application then welcome to the Xilinx Zynq SoC adventure.  The Zynq definitely is a great choice and has the benefits of being both a processor and an FPGA at the same time.

We have had Zynq SoCs at ELMG Digital Power for a about three years now and have been developing our competence.  We have built up a Linux system on them in the past on one dev board.  We are in the process of rebuilding it for another board for use with an LCD application. We are at the end of the process of moving our Spartan 6 IP cores onto 7 series (including Zynqs) for use in newer designs using the Vivado toolchain.  We are also in the process of becoming certified Xilinx engineers through the Xilinx Alliance Program (XAP).  This includes a large amount of training on the Zynqs directly from Xilinx.

 

XAP Membership brings Zynq AMP benefits to ELMG Digital Power

ELMG Digital Power Membership of the Xilinx Alliance Program, XAP, means Zynq Asymmetric Multiprocessing know how and expertise.

Asymmetric Multiprocessing AMP

Asymmetric Multiprocessing a really powerful way of getting the best of both worlds (RTOS for real-time performance, Linux for ease of use, HMI and communications) on the one device.  There are some pitfalls of using an RTOS for complex communication and Linux is not real-time.   It is not trivial and comes with quite a few pitfalls and things that you must take care of.  We have made some of these pitfalls so can help you with avoiding them.

These include the boot process and boot order as well as assigning which core is the ‘master’ and which is the ‘slave’.  One of the main things to consider and plan out in an AMP system is resource allocation.  Each core will need its own RAM whilst there must also be some shared RAM.  Inter-processor communications will also need to be considered as well as peripheral access (both allocated and shared).  Level 2 cache use also becomes more complicated.  With correct planning and execution however, the Zynq AMP is the powerful tool that you need. Making full use of the capability is critical in getting a successful control system.

One of the great things about the Zynq System on Chip Asymmetric Multiprocessing AMP, is that certain engineers can do certain roles without knowing much about the Zynq as a whole.  The HDL engineer can design modules with only knowing about the logic side and a software engineer can write code only knowing about the processor side.  However, it is the bit in between which makes the Zynq so powerful and provides the magic that makes it run as a whole SoC.  Getting data from the logic to the software in a timely manner is not as trivial as it sounds.  One of the issues to be aware of is cache coherence.  This is because the time it takes for the data to reach the software can range from clk cycles to hundreds even thousands of clock cycles depending on the interface used (for example it takes 25 clock cycles just to get to level 2 cache and many more if a DDR fetch is required).  In control systems, this latency is important and choosing the correct interfaces for suitable data flow latency is key.

There are many of things to cover on the Zynq.  This include  partitioning who does what, logic or software?

Demonstration of a simple car dash on 7z010 Zynq SoC

Saturday, August 29th, 2015

This demonstration of a simple car dash on 7z010 Zynq SoC from Xilinx implements an touch screen automotive car dash cluster with speedometer and rev counter.

 

The hardware target is the Avnet MicroZed which is mounted on a carrier board.  The LCD is a seven inch touch display.

 

We put this together using the Xilinx Vivado Design Suite.

Contact us for touch screen and display solutions using Zynq.

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Contact us for touch screen and display solutions using Zynq.